\section{Conclusion}
In this work, we designed a TSV-first Known-Good-Stack test scheme for reducing 3D ICs test time and increasing yield. Our design is based on the TSV cluster structure. We presented a breadth-first binary searching algorithm for BIST design. This algorithm found the failed TSVs within a few cycles. The defect TSVs were replaced by redundant resources with small overhead. The BIST algorithm and circuit achieved high testing speed and can decrease the testing time to under 20 cycles. This methodology worked for a large range of defect rate and significantly increased the overall TSV cluster yield. When the TSV cluster yield is over 30\%, less than 6 redundant TSVs can fix all the defects in most case.  



